aprs.aialfa

F4MUZ-1

Ayrıştırılmamış paketler

Satırlar APRS-IS'ten geldiği haliyle, en yenisi üstte. Son 7 gün saklanır.

  1. :F4MUZ-1>APLRG1,F4KLD-4*,qAR,F4KOL-4:=L8JIWNnVga !GLoRa APRS bridge
  2. :F4MUZ-1>APLRG1,F4KLD-4*,qAR,F5MDY-10:=L8JIWNnVga !GLoRa APRS bridge
  3. :F4MUZ-1>APLRG1,F4KLD-4*,qAR,F5MDY-10:=L8JIWNnVga !GLoRa APRS bridge
  4. :F4MUZ-1>APLRG1,F4KLD-4*,qAR,F4KOL-4:=L8JIWNnVga !GLoRa APRS bridge
  5. :F4MUZ-1>APLRG1,F4KLD-4*,qAR,F4KOL-4:=L8JIWNnVga !GLoRa APRS bridge
  6. :F4MUZ-1>APLRG1,F4KLD-4*,qAR,F4INI-10:=L8JIWNnVga !GLoRa APRS bridge
  7. :F4MUZ-1>APLRG1,F4KLD-4*,qAR,F4KOL-4:=L8JIWNnVga !GLoRa APRS bridge
  8. :F4MUZ-1>APLRG1,F4KLD-4*,qAR,F1ZDB-13:=L8JIWNnVga !GLoRa APRS bridge
  9. :F4MUZ-1>APLRG1,F4KLD-4*,qAR,F4KOL-4:=L8JIWNnVga !GLoRa APRS bridge
  10. :F4MUZ-1>APLRG1,F4KLD-4*,qAR,F4KOL-4:=L8JIWNnVga !GLoRa APRS bridge
  11. :F4MUZ-1>APLRG1,F4KLD-4*,qAR,F4INI-10:=L8JIWNnVga !GLoRa APRS bridge
  12. :F4MUZ-1>APLRG1,F4KLD-4*,qAR,F4KOL-4:=L8JIWNnVga !GLoRa APRS bridge
  13. :F4MUZ-1>APLRG1,F4KLD-4*,qAR,F4KOL-4:=L8JIWNnVga !GLoRa APRS bridge
  14. :F4MUZ-1>APLRG1,F4KLD-4*,qAR,F4INI-10:=L8JIWNnVga !GLoRa APRS bridge
  15. :F4MUZ-1>APLRG1,F4KLD-4*,qAR,F5MDY-10:=L8JIWNnVga !GLoRa APRS bridge
  16. :F4MUZ-1>APLRG1,F4KLD-4*,qAR,F5MDY-10:=L8JIWNnVga !GLoRa APRS bridge
  17. :F4MUZ-1>APLRG1,F4KLD-4*,qAR,F5MDY-10:=L8JIWNnVga !GLoRa APRS bridge
  18. :F4MUZ-1>APLRG1,F4KLD-4*,qAR,F5MDY-10:=L8JIWNnVga !GLoRa APRS bridge
  19. :F4MUZ-1>APLRG1,F4KLD-4*,qAR,F1ZDB-13:=L8JIWNnVga !GLoRa APRS bridge
  20. :F4MUZ-1>APLRG1,F4KLD-4*,qAR,F5MDY-10:=L8JIWNnVga !GLoRa APRS bridge
  21. :F4MUZ-1>APLRG1,F4KLD-4*,qAR,F5MDY-10:=L8JIWNnVga !GLoRa APRS bridge
  22. :F4MUZ-1>APLRG1,F4KLD-4*,qAR,F4KOL-4:=L8JIWNnVga !GLoRa APRS bridge
  23. :F4MUZ-1>APLRG1,F4KLD-4*,qAR,F5MDY-10:=L8JIWNnVga !GLoRa APRS bridge
  24. :F4MUZ-1>APLRG1,F4KLD-4*,qAR,F4KOL-4:=L8JIWNnVga !GLoRa APRS bridge
  25. :F4MUZ-1>APLRG1,F4KLD-4*,qAR,F4KOL-4:=L8JIWNnVga !GLoRa APRS bridge
  26. :F4MUZ-1>APLRG1,F4KLD-4*,qAR,F4KOL-4:=L8JIWNnVga !GLoRa APRS bridge
  27. :F4MUZ-1>APLRG1,F4KLD-4*,qAR,F4KOL-4:=L8JIWNnVga !GLoRa APRS bridge
  28. :F4MUZ-1>APLRG1,F4KLD-4*,qAR,F4KOL-4:=L8JIWNnVga !GLoRa APRS bridge
  29. :F4MUZ-1>APLRG1,F4KLD-4*,qAR,F4KOL-4:=L8JIWNnVga !GLoRa APRS bridge
  30. :F4MUZ-1>APLRG1,F4KLD-4*,qAR,F4KOL-4:=L8JIWNnVga !GLoRa APRS bridge
  31. :F4MUZ-1>APLRG1,F4KLD-4*,qAR,F4KOL-4:=L8JIWNnVga !GLoRa APRS bridge
  32. :F4MUZ-1>APLRG1,F4KLD-4*,qAR,F5MDY-10:=L8JIWNnVga !GLoRa APRS bridge
  33. :F4MUZ-1>APLRG1,F4KLD-4*,qAR,F4KOL-4:=L8JIWNnVga !GLoRa APRS bridge
  34. :F4MUZ-1>APLRG1,F4KLD-4*,qAR,F4KOL-4:=L8JIWNnVga !GLoRa APRS bridge
  35. :F4MUZ-1>APLRG1,F4KLD-4*,qAR,F4KOL-4:=L8JIWNnVga !GLoRa APRS bridge
  36. :F4MUZ-1>APLRG1,F4KLD-4*,qAR,F4KOL-4:=L8JIWNnVga !GLoRa APRS bridge
  37. :F4MUZ-1>APLRG1,F4KLD-4*,qAR,F4KOL-4:=L8JIWNnVga !GLoRa APRS bridge
  38. :F4MUZ-1>APLRG1,F4KLD-4*,qAR,F4KOL-4:=L8JIWNnVga !GLoRa APRS bridge
  39. :F4MUZ-1>APLRG1,F4KLD-4*,qAR,F4KOL-4:=L8JIWNnVga !GLoRa APRS bridge
  40. :F4MUZ-1>APLRG1,F4KLD-4*,qAR,F4KOL-4:=L8JIWNnVga !GLoRa APRS bridge
  41. :F4MUZ-1>APLRG1,F4KLD-4*,qAR,F5MDY-10:=L8JIWNnVga !GLoRa APRS bridge
  42. :F4MUZ-1>APLRG1,F4KLD-4*,qAR,F1ZDB-13:=L8JIWNnVga !GLoRa APRS bridge
  43. :F4MUZ-1>APLRG1,F4KLD-4*,qAR,F5MDY-10:=L8JIWNnVga !GLoRa APRS bridge
  44. :F4MUZ-1>APLRG1,F4KLD-4*,qAR,F4KOL-4:=L8JIWNnVga !GLoRa APRS bridge
  45. :F4MUZ-1>APLRG1,F4KLD-4*,qAR,F4KOL-4:=L8JIWNnVga !GLoRa APRS bridge
  46. :F4MUZ-1>APLRG1,F4KLD-4*,qAR,F4KOL-4:=L8JIWNnVga !GLoRa APRS bridge
  47. :F4MUZ-1>APLRG1,F4KLD-4*,qAR,F5MDY-10:=L8JIWNnVga !GLoRa APRS bridge
  48. :F4MUZ-1>APLRG1,F4KLD-4*,qAR,F4KOL-4:=L8JIWNnVga !GLoRa APRS bridge
  49. :F4MUZ-1>APLRG1,F4KLD-4*,qAR,F4KOL-4:=L8JIWNnVga !GLoRa APRS bridge
  50. :F4MUZ-1>APLRG1,F4KLD-4*,qAR,F1ZDB-13:=L8JIWNnVga !GLoRa APRS bridge
  51. :F4MUZ-1>APLRG1,F4KLD-4*,qAR,F4KOL-4:=L8JIWNnVga !GLoRa APRS bridge
  52. :F4MUZ-1>APLRG1,F4KLD-4*,qAR,F4KOL-4:=L8JIWNnVga !GLoRa APRS bridge
  53. :F4MUZ-1>APLRG1,F4KLD-4*,qAR,F1ZDB-13:=L8JIWNnVga !GLoRa APRS bridge
  54. :F4MUZ-1>APLRG1,F4KLD-4*,qAR,F5MDY-10:=L8JIWNnVga !GLoRa APRS bridge
  55. :F4MUZ-1>APLRG1,F4MLV-10*,qAO,F6DEV-10:=L8JIWNnVga !GLoRa APRS bridge
  56. :F4MUZ-1>APLRG1,F4MLV-10*,qAO,F6DEV-10:=L8JIWNnVga !GLoRa APRS bridge
  57. :F4MUZ-1>APLRG1,F4MLV-10*,qAR,F4INI-10:=L8JIWNnVga !GLoRa APRS bridge
  58. :F4MUZ-1>APLRG1,F4MLV-10*,qAO,F5BYL-10:=L8JIWNnVga !GLoRa APRS bridge
  59. :F4MUZ-1>APLRG1,F4KLD-4*,qAR,F4KOL-4:=L8JIWNnVga !GLoRa APRS bridge
  60. :F4MUZ-1>APLRG1,F4KLD-4*,qAR,F5MDY-10:=L8JIWNnVga !GLoRa APRS bridge
  61. :F4MUZ-1>APLRG1,F4KLD-4*,qAR,F4KOL-4:=L8JIWNnVga !GLoRa APRS bridge
  62. :F4MUZ-1>APLRG1,F4KLD-4*,qAR,F5MDY-10:=L8JIWNnVga !GLoRa APRS bridge
  63. :F4MUZ-1>APLRG1,F4KLD-4*,qAR,F5MDY-10:=L8JIWNnVga !GLoRa APRS bridge
  64. :F4MUZ-1>APLRG1,F4KLD-4*,qAR,F5MDY-10:=L8JIWNnVga !GLoRa APRS bridge
  65. :F4MUZ-1>APLRG1,F4KLD-4*,qAR,F5MDY-10:=L8JIWNnVga !GLoRa APRS bridge
  66. :F4MUZ-1>APLRG1,F4KLD-4*,qAR,F4KOL-4:=L8JIWNnVga !GLoRa APRS bridge
  67. :F4MUZ-1>APLRG1,F4MLV-10*,qAO,F6DEV-10:=L8JIWNnVga !GLoRa APRS bridge
  68. :F4MUZ-1>APLRG1,F4KLD-4*,qAR,F4KOL-4:=L8JIWNnVga !GLoRa APRS bridge
  69. :F4MUZ-1>APLRG1,F4KLD-4*,qAR,F1ZDB-13:=L8JIWNnVga !GLoRa APRS bridge
  70. :F4MUZ-1>APLRG1,F4KLD-4*,qAR,F1ZDB-13:=L8JIWNnVga !GLoRa APRS bridge
  71. :F4MUZ-1>APLRG1,F4KLD-4*,qAR,F4KOL-4:=L8JIWNnVga !GLoRa APRS bridge
  72. :F4MUZ-1>APLRG1,F4KLD-4*,qAR,F5MDY-10:=L8JIWNnVga !GLoRa APRS bridge
  73. :F4MUZ-1>APLRG1,F4KLD-4*,qAR,F1ZDB-13:=L8JIWNnVga !GLoRa APRS bridge
  74. :F4MUZ-1>APLRG1,F4KLD-4*,qAR,F5MDY-10:=L8JIWNnVga !GLoRa APRS bridge
  75. :F4MUZ-1>APLRG1,F4KLD-4*,qAR,F5MDY-10:=L8JIWNnVga !GLoRa APRS bridge
  76. :F4MUZ-1>APLRG1,F4KLD-4*,qAR,F5MDY-10:=L8JIWNnVga !GLoRa APRS bridge
  77. :F4MUZ-1>APLRG1,F4KLD-4*,qAR,F5MDY-10:=L8JIWNnVga !GLoRa APRS bridge
  78. :F4MUZ-1>APLRG1,F4KLD-4*,qAR,F5MDY-10:=L8JIWNnVga !GLoRa APRS bridge
  79. :F4MUZ-1>APLRG1,F4KLD-4*,qAR,F5MDY-10:=L8JIWNnVga !GLoRa APRS bridge
  80. :F4MUZ-1>APLRG1,F4KLD-4*,qAR,F5MDY-10:=L8JIWNnVga !GLoRa APRS bridge
  81. :F4MUZ-1>APLRG1,F4KLD-4*,qAR,F1ZDB-13:=L8JIWNnVga !GLoRa APRS bridge
  82. :F4MUZ-1>APLRG1,F4KLD-4*,qAR,F5MDY-10:=L8JIWNnVga !GLoRa APRS bridge
  83. :F4MUZ-1>APLRG1,F4KLD-4*,qAR,F5MDY-10:=L8JIWNnVga !GLoRa APRS bridge
  84. :F4MUZ-1>APLRG1,F4KLD-4*,qAR,F5MDY-10:=L8JIWNnVga !GLoRa APRS bridge
  85. :F4MUZ-1>APLRG1,F4KLD-4*,qAR,F5MDY-10:=L8JIWNnVga !GLoRa APRS bridge
  86. :F4MUZ-1>APLRG1,F4KLD-4*,qAR,F5MDY-10:=L8JIWNnVga !GLoRa APRS bridge
  87. :F4MUZ-1>APLRG1,F4KLD-4*,qAR,F5MDY-10:=L8JIWNnVga !GLoRa APRS bridge
  88. :F4MUZ-1>APLRG1,F4KLD-4*,qAR,F5MDY-10:=L8JIWNnVga !GLoRa APRS bridge
  89. :F4MUZ-1>APLRG1,F4KLD-4*,qAR,F5MDY-10:=L8JIWNnVga !GLoRa APRS bridge
  90. :F4MUZ-1>APLRG1,F4KLD-4*,qAR,F5MDY-10:=L8JIWNnVga !GLoRa APRS bridge
  91. :F4MUZ-1>APLRG1,F4KLD-4*,qAR,F5MDY-10:=L8JIWNnVga !GLoRa APRS bridge
  92. :F4MUZ-1>APLRG1,F4KLD-4*,qAR,F5MDY-10:=L8JIWNnVga !GLoRa APRS bridge
  93. :F4MUZ-1>APLRG1,F4KLD-4*,qAR,F4KOL-4:=L8JIWNnVga !GLoRa APRS bridge
  94. :F4MUZ-1>APLRG1,F4KLD-4*,qAR,F5MDY-10:=L8JIWNnVga !GLoRa APRS bridge
  95. :F4MUZ-1>APLRG1,F4KLD-4*,qAR,F5MDY-10:=L8JIWNnVga !GLoRa APRS bridge
  96. :F4MUZ-1>APLRG1,F4KLD-4*,qAR,F5MDY-10:=L8JIWNnVga !GLoRa APRS bridge
  97. :F4MUZ-1>APLRG1,F4KLD-4*,qAR,F5MDY-10:=L8JIWNnVga !GLoRa APRS bridge
  98. :F4MUZ-1>APLRG1,F4KLD-4*,qAR,F5MDY-10:=L8JIWNnVga !GLoRa APRS bridge
  99. :F4MUZ-1>APLRG1,F4KLD-4*,qAR,F5MDY-10:=L8JIWNnVga !GLoRa APRS bridge
  100. :F4MUZ-1>APLRG1,F4KLD-4*,qAR,F5MDY-10:=L8JIWNnVga !GLoRa APRS bridge
  101. :F4MUZ-1>APLRG1,F4KLD-4*,qAR,F4KOL-4:=L8JIWNnVga !GLoRa APRS bridge
  102. :F4MUZ-1>APLRG1,F4KLD-4*,qAR,F5MDY-10:=L8JIWNnVga !GLoRa APRS bridge
  103. :F4MUZ-1>APLRG1,F4KLD-4*,qAR,F5MDY-10:=L8JIWNnVga !GLoRa APRS bridge
  104. :F4MUZ-1>APLRG1,F4KLD-4*,qAR,F5MDY-10:=L8JIWNnVga !GLoRa APRS bridge
  105. :F4MUZ-1>APLRG1,F4KLD-4*,qAR,F5MDY-10:=L8JIWNnVga !GLoRa APRS bridge
  106. :F4MUZ-1>APLRG1,F4KLD-4*,qAR,F5MDY-10:=L8JIWNnVga !GLoRa APRS bridge
  107. :F4MUZ-1>APLRG1,F4KLD-4*,qAR,F5MDY-10:=L8JIWNnVga !GLoRa APRS bridge
  108. :F4MUZ-1>APLRG1,F4KLD-4*,qAR,F4KOL-4:=L8JIWNnVga !GLoRa APRS bridge
  109. :F4MUZ-1>APLRG1,F4KLD-4*,qAR,F5MDY-10:=L8JIWNnVga !GLoRa APRS bridge
  110. :F4MUZ-1>APLRG1,F4KLD-4*,qAR,F5MDY-10:=L8JIWNnVga !GLoRa APRS bridge
  111. :F4MUZ-1>APLRG1,F4KLD-4*,qAR,F5MDY-10:=L8JIWNnVga !GLoRa APRS bridge
  112. :F4MUZ-1>APLRG1,F4KLD-4*,qAR,F5MDY-10:=L8JIWNnVga !GLoRa APRS bridge
  113. :F4MUZ-1>APLRG1,F4KLD-4*,qAR,F5MDY-10:=L8JIWNnVga !GLoRa APRS bridge
  114. :F4MUZ-1>APLRG1,F4KLD-4*,qAR,F1ZDB-13:=L8JIWNnVga !GLoRa APRS bridge
  115. :F4MUZ-1>APLRG1,F4KLD-4*,qAR,F4KOL-4:=L8JIWNnVga !GLoRa APRS bridge
  116. :F4MUZ-1>APLRG1,F4KLD-4*,qAR,F4KOL-4:=L8JIWNnVga !GLoRa APRS bridge
  117. :F4MUZ-1>APLRG1,F4KLD-4*,qAR,F5MDY-10:=L8JIWNnVga !GLoRa APRS bridge
  118. :F4MUZ-1>APLRG1,F4KLD-4*,qAR,F4KOL-4:=L8JIWNnVga !GLoRa APRS bridge
  119. :F4MUZ-1>APLRG1,F4KLD-4*,qAR,F5MDY-10:=L8JIWNnVga !GLoRa APRS bridge
  120. :F4MUZ-1>APLRG1,F4KLD-4*,qAR,F5MDY-10:=L8JIWNnVga !GLoRa APRS bridge
  121. :F4MUZ-1>APLRG1,F4KLD-4*,qAR,F4KOL-4:=L8JIWNnVga !GLoRa APRS bridge
  122. :F4MUZ-1>APLRG1,F4KLD-4*,qAR,F5MDY-10:=L8JIWNnVga !GLoRa APRS bridge
  123. :F4MUZ-1>APLRG1,F4KLD-4*,qAR,F4KOL-4:=L8JIWNnVga !GLoRa APRS bridge
  124. :F4MUZ-1>APLRG1,F4KLD-4*,qAR,F5MDY-10:=L8JIWNnVga !GLoRa APRS bridge
  125. :F4MUZ-1>APLRG1,F4KLD-4*,qAR,F5MDY-10:=L8JIWNnVga !GLoRa APRS bridge
  126. :F4MUZ-1>APLRG1,F4KLD-4*,qAR,F5MDY-10:=L8JIWNnVga !GLoRa APRS bridge
  127. :F4MUZ-1>APLRG1,F4KLD-4*,qAR,F4KOL-4:=L8JIWNnVga !GLoRa APRS bridge
  128. :F4MUZ-1>APLRG1,F4KLD-4*,qAR,F4KOL-4:=L8JIWNnVga !GLoRa APRS bridge
  129. :F4MUZ-1>APLRG1,F4KLD-4*,qAR,F5MDY-10:=L8JIWNnVga !GLoRa APRS bridge
  130. :F4MUZ-1>APLRG1,F4KLD-4*,qAR,F4KOL-4:=L8JIWNnVga !GLoRa APRS bridge
  131. :F4MUZ-1>APLRG1,F4KLD-4*,qAR,F4KOL-4:=L8JIWNnVga !GLoRa APRS bridge
  132. :F4MUZ-1>APLRG1,F4KLD-4*,qAR,F1ZDB-13:=L8JIWNnVga !GLoRa APRS bridge
  133. :F4MUZ-1>APLRG1,F4KLD-4*,qAR,F5MDY-10:=L8JIWNnVga !GLoRa APRS bridge
  134. :F4MUZ-1>APLRG1,F4KLD-4*,qAR,F4KOL-4:=L8JIWNnVga !GLoRa APRS bridge
  135. :F4MUZ-1>APLRG1,F4KLD-4*,qAR,F4KOL-4:=L8JIWNnVga !GLoRa APRS bridge
  136. :F4MUZ-1>APLRG1,F4KLD-4*,qAR,F4KOL-4:=L8JIWNnVga !GLoRa APRS bridge
  137. :F4MUZ-1>APLRG1,F4MLV-10*,qAO,F6DEV-10:=L8JIWNnVga !GLoRa APRS bridge
  138. :F4MUZ-1>APLRG1,F4KLD-4*,qAR,F4KOL-4:=L8JIWNnVga !GLoRa APRS bridge
  139. :F4MUZ-1>APLRG1,F4KLD-4*,qAR,F4KOL-4:=L8JIWNnVga !GLoRa APRS bridge
  140. :F4MUZ-1>APLRG1,F4KLD-4*,qAR,F4KOL-4:=L8JIWNnVga !GLoRa APRS bridge
  141. :F4MUZ-1>APLRG1,F4KLD-4*,qAR,F4KOL-4:=L8JIWNnVga !GLoRa APRS bridge
  142. :F4MUZ-1>APLRG1,F4KLD-4*,qAR,F4KOL-4:=L8JIWNnVga !GLoRa APRS bridge
  143. :F4MUZ-1>APLRG1,F4KLD-4*,qAR,F5MDY-10:=L8JIWNnVga !GLoRa APRS bridge
  144. :F4MUZ-1>APLRG1,F4KLD-4*,qAR,F5MDY-10:=L8JIWNnVga !GLoRa APRS bridge
  145. :F4MUZ-1>APLRG1,F4KLD-4*,qAR,F4KOL-4:=L8JIWNnVga !GLoRa APRS bridge
  146. :F4MUZ-1>APLRG1,F4KLD-4*,qAR,F5MDY-10:=L8JIWNnVga !GLoRa APRS bridge
  147. :F4MUZ-1>APLRG1,F4KLD-4*,qAR,F5MDY-10:=L8JIWNnVga !GLoRa APRS bridge
  148. :F4MUZ-1>APLRG1,F4KLD-4*,qAR,F4KOL-4:=L8JIWNnVga !GLoRa APRS bridge
  149. :F4MUZ-1>APLRG1,F4KLD-4*,qAR,F5MDY-10:=L8JIWNnVga !GLoRa APRS bridge
  150. :F4MUZ-1>APLRG1,F4KLD-4*,qAR,F5MDY-10:=L8JIWNnVga !GLoRa APRS bridge
  151. :F4MUZ-1>APLRG1,F4KLD-4*,qAR,F5MDY-10:=L8JIWNnVga !GLoRa APRS bridge
  152. :F4MUZ-1>APLRG1,F4KLD-4*,qAR,F5MDY-10:=L8JIWNnVga !GLoRa APRS bridge
  153. :F4MUZ-1>APLRG1,F4KLD-4*,qAR,F5MDY-10:=L8JIWNnVga !GLoRa APRS bridge
  154. :F4MUZ-1>APLRG1,F4KLD-4*,qAR,F5MDY-10:=L8JIWNnVga !GLoRa APRS bridge
  155. :F4MUZ-1>APLRG1,F4KLD-4*,qAR,F5MDY-10:=L8JIWNnVga !GLoRa APRS bridge
  156. :F4MUZ-1>APLRG1,F4KLD-4*,qAR,F5MDY-10:=L8JIWNnVga !GLoRa APRS bridge
  157. :F4MUZ-1>APLRG1,F4KLD-4*,qAR,F5MDY-10:=L8JIWNnVga !GLoRa APRS bridge
  158. :F4MUZ-1>APLRG1,F4KLD-4*,qAR,F5MDY-10:=L8JIWNnVga !GLoRa APRS bridge
  159. :F4MUZ-1>APLRG1,F4KLD-4*,qAR,F5MDY-10:=L8JIWNnVga !GLoRa APRS bridge
  160. :F4MUZ-1>APLRG1,F4KLD-4*,qAR,F5MDY-10:=L8JIWNnVga !GLoRa APRS bridge
  161. :F4MUZ-1>APLRG1,F4KLD-4*,qAR,F5MDY-10:=L8JIWNnVga !GLoRa APRS bridge
  162. :F4MUZ-1>APLRG1,F4KLD-4*,qAR,F5MDY-10:=L8JIWNnVga !GLoRa APRS bridge
  163. :F4MUZ-1>APLRG1,F4KLD-4*,qAR,F5MDY-10:=L8JIWNnVga !GLoRa APRS bridge
  164. :F4MUZ-1>APLRG1,F4KLD-4*,qAR,F5MDY-10:=L8JIWNnVga !GLoRa APRS bridge
  165. :F4MUZ-1>APLRG1,F4KLD-4*,qAR,F5MDY-10:=L8JIWNnVga !GLoRa APRS bridge
  166. :F4MUZ-1>APLRG1,F4KLD-4*,qAR,F5MDY-10:=L8JIWNnVga !GLoRa APRS bridge
  167. :F4MUZ-1>APLRG1,F4KLD-4*,qAR,F5MDY-10:=L8JIWNnVga !GLoRa APRS bridge
  168. :F4MUZ-1>APLRG1,F4KLD-4*,qAR,F5MDY-10:=L8JIWNnVga !GLoRa APRS bridge
  169. :F4MUZ-1>APLRG1,F4KLD-4*,qAR,F5MDY-10:=L8JIWNnVga !GLoRa APRS bridge
  170. :F4MUZ-1>APLRG1,F4KLD-4*,qAR,F5MDY-10:=L8JIWNnVga !GLoRa APRS bridge
  171. :F4MUZ-1>APLRG1,F4KLD-4*,qAR,F1ZDB-13:=L8JIWNnVga !GLoRa APRS bridge